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3-Axis Digital Compass IC HMC5843
The Honeywell HMC5843 is a surface mount multi-chip module designed for low field magnetic sensing with a digital interface for applications such as low cost compassing and magnetometry. The HMC5843 includes our state of the art 1043 series magneto-resistive sensors plus Honeywell developed ASIC containing amplification, strap drivers, offset cancellation, 12-bit ADC and an I C serial bus interface. The HMC5843 is in a 4.0 by 4.0 by 1.3mm surface mount leadless chip carrier ( CC). Applications for the L HMC5843 include Consumer Electronics, Auto Navigation Systems, Personal Navigation Devices, and Magnetometers.
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The HMC5843 utilizes Honeywell's Anisotropic Magnetoresistive (AMR) technology that provides advantages over other magnetic sensor technologies. The sensors feature precision in-axis sensitivity and linearity, solid-state construction with very low cross-axis sensitivity designed to measure both direction and magnitude of Earth's magnetic fields, from tens of micro-gauss to 6 gauss. Honeywell's Magnetic Sensors are among the most sensitive and reliable low-field sensors in the industry.
Honeywell continues to maintain product excellence and performance by introducing innovative solid-state magnetic sensor solutions. These are highly reliable, top performance products that are delivered when promised. Honeywell's magnetic sensor solutions provide real solutions you can count on.
FEATURES 4 4 4 4 4 4 4 4 4
3-Axis Magnetoresistive Sensors and ASIC in a Single Package Low Cost 4.0 x 4.0 x 1.3mm Low Height Profile LCC Surface Mount Package Low Voltage Operations (2.5 to 3.3V) Built-In Strap Drive Circuits I C Digital Interface Lead Free Package Construction Wide Magnetic Field Range (+/-6 Oe) Available in Tape & Reel Packaging
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BENEFITS
for Highly Integrated Products. Just Add a Micro4 Small SizeInterface, Plus Two External SMT Capacitors Controller
4 Designed for High Volume, Cost Sensitive OEM Designs 4 Easy to Assemble & Compatible with High Speed SMT Assembly 4 Compatible for Battery Powered Applications 4 Set/Reset and Offset Strap Drivers for Degaussing, Self Test, and Offset Compensation 4 Popular Two-Wire Serial Data Interface for Consumer Electronics 4 Complies with Current Environmental Standards 4 Sensors Can Be Used in Strong Magnetic Field Environments 4 High Volume OEM Assembly
HMC5843
SPECIFICATIONS (* Tested at 25C except stated otherwise.)
Characteristics Power Supply Supply Voltage Current Draw AVDD Referenced to AGND DVDD Referenced to DGND Sleep Mode (dual supplies) Idle Mode (dual supplies) Measurement Mode AVDD = 2.5 volts, DVDD = 1.8 volts Sleep Mode (single supply) Idle Mode (single supply) Measurement Mode AVDD = 2.5 volts Performance Field Range Cross-Axis Sensitivity Disturbing Field Max. Exposed Field Measurement Period I C Address
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Conditions*
Min
Typ
Max
Units
2.5 1.6 1.8 2.5 240 0.8 110 340 0.9
3.3 2.0 -
Volts Volts uA uA mA uA uA mA
Full scale (FS) - total applied field Cross field = 0.5 gauss, Happlied = 3 gauss Sensitivity starts to degrade. Use S/R pulse to restore sensitivity. No perming effect on zero reading Output Rate = 50Hz (10Hz typ.) 7-bit address 8-bit read address 8-bit write address
-4 0.2%
+4
gauss %FS/gauss
20 10000 0x1E 0x3D 0x3C -10 50 0.603 1.108 0.55 0.7 1.0 5 10 7 70 200 700 4.0 0.1 +10 10
gauss gauss msec hex hex hex % kilo-ohms Volts Volts gauss gauss % FS % kHz milli-gauss dB us V C C milli-grams
I C Rate I C bus pull-up I C Hysteresis
2 2
2
Controlled by I C Master Internal passive resistors Hysteresis of Schmitt trigger inputs on SCL and SDA - Fall (DVDD=1.8V) Rise (DVDD=1.8V)
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Self Test Mag Dynamic Range Linearity Gain Tolerance Bandwidth Resolution Signal-to Noise Ratio Turn-on Time General ESD Voltage Operating Temperature Storage Temperature Weight
Positive and Negative Bias Mode 3-bit gain control Full scale input range All gain/dynamic range settings -3dB point AVDD=3.0V, GN
Ambient Ambient, unbiased Nominal
-30 -40 50
85 125
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HMC5843
PIN CONFIGURATIONS
(Arrow indicates direction of applied field that generates a positive output voltage after a SET pulse.) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name SCL SDAP SCLP NC NC OFFP OFFN NC SETP SETN SVDD DGND C1 SETC DVDD VREN AGND AVDD DRDY SDA Description Serial Clock - I2C Master/Slave Clock Serial Data Pull-up Resistor - 50k-ohm to VDD Serial Clock Pull-up Resistor - 50k-ohm to VDD No Connection No Connection Offset Strap Positive Offset Strap Negative No Connection Set/Reset Strap Positive - S/R Capacitor (C2) Connection Set/Reset Strap Negative - Test Point Sensor Supply - Test Point Digital Supply Ground/Return Reservoir Capacitor (C1) Connection S/R Capacitor (C2) Connection - Driver Side Digital Positive Supply Voltage Regulator Enable, (GND = Dual Supply, AVDD = Single Supply) Analog Supply Ground/Return Analog Positive Supply Data Ready - Test Point Serial Data - I2C Master/Slave Data Table 1: Pin Configurations
SDAP 2 SCLP SCL 1 TP1 TP1 4 TP0
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5
SDA 20 DRDY 19 Z AVDD 18 AGND 17 VREN 16 X Y
6 7 8 9 10
OFFP OFFN NC SETP SETN
15 DVDD
14 SETC SETC
13 C1
12 DGND DGND
11 SVDD
HMC5843 - bottom view
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HMC5843
PACKAGE OUTLINES
PACKAGE DRAWING HMC5843 (20-PIN LPCC, dimensions in millimeters)
Pin 1
D3
D2
A
Sym A D
Min 1.20
Nom 4.0 BSC 2.25 0.25 x 20 pins 4.0 BSC 2.25 0.50 Basic 0.40 x 20 pins
Max 1.46
E2
E
D2 D3 E E2 e
L D
e HMC5843 - bottom view
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MOUNTING CONSIDERATIONS
The following is the recommend printed circuit board (PCB) footprint for the HMC5843. PCB Pad Definition and Traces The HMC5843 is a fine pitch LCC package with a 0.50mm pin pitch (spacing), with the pin pads defined as 0.40mm by 0.25mm in size. PCB pads are recommended to be oversized by 0.025mm from each pad for a short dimension oversize of 0.05mm. The interior PCB pad is recommended to be 0.05mm oversized per pin with an exterior oversize of 0.20mm for proper package centering and to permit test probing. Size the traces between the HMC5843 and the external capacitors (C1 and C2) to handle the 1 ampere peak current pulses with low voltage drop on the traces. Stencil Design and Solder Paste A 4 mil stencil and 100% paste coverage is recommended for the electrical contact pads. Pick and Place Placement is machine dependant and no restrictions are recommended, and have been tested with mechanical centering. Placement force should be equivalent 1206 SMT resistors and enough force should be used to squeeze the paste out from the package/contact pad overlap and to keep the package pin contacts vertical. Reflow and Rework No special profile is required for the HMC5843 and compatible with lead eutectic and lead-free solder paste reflow profiles. Honeywell recommends the adherence to solder paste manufacturer's guidelines. The HMC5843 may be reworked with soldering irons, but extreme care must be taken not to overheat the copper pads from the part's fiberglass substrate. Irons with a tip temperature no greater than 315C should be used. Excessive rework risks the copper pads pulling away into the molten solder. 4 www.honeywell.com
HMC5843
INTERNAL SCHEMATIC DIAGRAM
HMC5843
DUAL SUPPLY REFERENCE DESIGN
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HMC5843
SINGLE SUPPLY REFERENCE DESIGN
BASIC DEVICE OPERATION
Anisotropic Magneto-Resistive Sensors The Honeywell HMC5843 magnetoresistive sensor circuit is a trio of sensors and application specific support circuits to measure magnetic fields. With power supply applied, the sensor converts any incident magnetic field in the sensitive axis directions to a differential voltage output. The magnetoresistive sensors are made of a nickel-iron (Permalloy) thin-film and patterned as a resistive strip element. In the presence of a magnetic field, a change in the bridge resistive elements causes a corresponding change in voltage across the bridge outputs. These resistive elements are aligned together to have a common sensitive axis (indicated by arrows on the pinouts) that will provide positive voltage change with magnetic fields increasing in the sensitive direction. Because the output only is in proportion to the one-dimensional axis (the principle of anisotropy) and its magnitude, additional sensor bridges placed at orthogonal directions permit accurate measurement of arbitrary field direction. Self Test An offset strap is designed for self test function. The offset strap measures nominally 13 ohms, and requires 10mA for each gauss of induced field. The straps will easily handle currents to buck or boost fields through the 4 gauss linear measurement range, but designers should note the extreme thermal heating on the sensor die when doing so.
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HMC5843
Power Management This device is capable of operating with a single supply (AVDD) or dual supplies (AVDD and DVDD). Pin VREN makes this selection by enabling the internal digital supply voltage regulator. When VREN is tied to AVDD, the device is in single supply operation; this device is powered from AVDD; and the internal voltage regulator is enabled. When VREN is tied to AGND this devices operates with both AVDD and DVDD as supplies. The table below shows the modes available at the various power supply conditions. DVDD High AVDD High Pin VREN AGND Modes Supported All, except Off Description Internal voltage regulator: Disabled. Digital I/O pins: Range from DGND to DVDD. Device fully functional. Digital logic blocks are powered from DVDD supply, including all onboard clocks. Internal voltage regulator: Disabled. Digital I/O pins: Range from DGND to DVDD. Device Measurement functionality not supported. 2 Device I C bus and register access supported. Internal voltage regulator: Enabled Digital I/O pins: Range from AGND to AVDD Device fully functional. Digital logic blocks are powered through on-board regulator. Device in off mode.
High
Low
AGND
Idle
Internally regulated
High
AVDD
All, except Off
Low
Low
--
Off
Table 2: Operational Modes and Supply States
Note the continuous current draw versus data update rate in micro-amperes shown in the graph below. Under 10Hz, the current stays below 1mA.
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HMC5843
Voltage Regulator This ASIC has an internal voltage regulator which, depending on the application needs, may be used instead of supplying voltage to pin DVDD. If DVDD pin is used, the internal voltage regulator is not engaged. When both supplies are used, DVDD is typically high before AVDD, but no latch-up conditions will exist if DVDD is brought high after AVDD. Power on Reset Power on reset (POR) circuit shall return the device to the power-on default state. All registers shall be returned to their default values. Circuitry shall return to it default state, such as, but not limited to: MUX channel, ADC state machine, and bias current. I C Interface Control of this device is carried out via the I C bus. This device will be connected to this bus as a slave device under the control of a master device, such as the processor. This device shall be compliant with I C-Bus Specification, document number: 9398 393 40011. As an I C compatible 2 device, this device has a 7-bit serial address and supports I C protocols. This device shall support standard and fast modes, 100kHz and 400kHz respectively, but cannot support the high speed mode (Hs). External pull-up resistors are required to support these standard and fast speed modes. Depending on the application, the internal pull-ups may be 2 used to support slower data speeds than specified by I C standards. This device does not contain 50nsec spike 2 suppression as required by fast mode operation in the I C-Bus Specification, "Table 4 Characteristics of the SDA and 2 SCL I/O stages for F/S-mode I C-bus devices". Activities required by the master (register read and write) have priority over internal activities, such as the measurement. 2 The purpose of this priority is to not keep the master waiting and the I C bus engaged for longer than necessary. I C Pull-up Resistors Pull-up resistors are placed on the two I C bus lines. Typically these resistors are off-chip, but, to conserve board space in specific low clock speed applications, they are internal to this device. Internal Clock The device has an internal clock for internal digital logic functions and timing management. H-Bridge for Set/Reset Strap Drive The ASIC contains large switching FETs capable of delivering a large but brief pulse to the Set / Reset strap of the sensor. This strap is largely a resistive load.
2 2 2 2 2 2
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HMC5843
Charge Current Limit The current that reservoir capacitor (C1) can draw when charging is limited. When using dual supplies this device shall limit the current drawn from DVDD source to charge this capacitor. When only a single supply is used, Pin DVDD is externally tied to pin C1. In this configuration, current is still limited. For example, the internal voltage regulator will limit this current draw. Bias Current Generator The bias current generator is used to apply a bias current to the offset strap of the magneto-resistive sensor, which creates an artificial magnetic field bias on the sensor. This function is enabled and the polarity is set by bits MS[n] in the configuration register. The bias current generator generates dc current supplied from the AVDD supply.
MODES OF OPERATION
This device has several modes whose primary purpose is power management. This section describes these modes. Continuous-Measurement Mode During continuous-measurement mode, the device continuously makes measurements and places measured data in data output registers. Settings in the configuration register affect the data output rate (bits DO[n]), the measurement configuration (bits MS[n]), and the gain (bits GN[n]) when in continuous-measurement mode. To conserve current between measurements, the device is placed in a state similar to idle mode, but the mode is not changed to idle mode. That is, MD[n] bits are unchanged. Data can be re-read from the data output registers if necessary; however, if the master does not ensure that the data register is accessed before the completion of the next measurement, the new 2 measurement may be lost. All registers maintain values while in continuous-measurement mode. The I C bus is enabled for use by other devices on the network in while continuous-measurement mode. Single-Measurement Mode This is the default single supply power-up mode. In dual supply configuration this is the default mode when AVDD goes high. During single-measurement mode, the device makes a single measurement and places the measured data in data output registers. Settings in the configuration register affect the measurement configuration (bits MS[n]), and the gain (bits GN[n]) when in single-measurement mode. After the measurement is complete and output data registers are updated, the device is placed sleep mode, and the mode register is changed to sleep mode by setting MD[n] bits. All 2 registers maintain v alues while in single-measurement mode. The I C bus is enabled for use by other devices on the network while in single-measurement mode. Idle Mode During this mode the device is accessible through the I C bus, but major sources of power consumption are disabled, such as, but not limited to, the ADC, the amplifier, the SVDD pin, and the sensor bias current. All registers maintain 2 values while in idle mode. The I C bus is enabled for use by other devices on the network while in idle mode. Sleep Mode This is the default dual supply power-up mode when only DVDD goes high and AVDD remains low. During sleep mode 2 the device functionality is limited to listening to the I C bus. The internal clock is not running and register values are not maintained while in sleep mode. The only functionality that exists during this mode is the device is able to recognize and 2 execute any instructions specific to this device but does not change from sleep mode due to other traffic on the I C bus. 2 The I C bus is enabled for use by other devices on the network while in sleep mode. This mode has two practical differences from idle mode. First this state will create less noise on system since the clock is disabled, and secondly this state is a lower current consuming state since the clock is disabled. Off Mode During off mode device is off. No device functionality exists. Both AVDD and DVDD are low. The I C bus is enabled for 2 use by other devices on the network in off mode. In this mode the I C pins shall be in a high impedance state.
2 2
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HMC5843
REGISTERS
This device is controlled and configured via a number of on-chip registers, which are described in this section. In the following descriptions, set implies a logic 1, and reset or clear implies a logic 0, unless stated otherwise. Register List The table below lists the registers and their access. All address locations are 8 bits. Address Location 00 01 02 03 04 05 06 07 08 09 10 11 12 Name Configuration Register A Configuration Register B Mode Register Data Output X MSB Register Data Output X LSB Register Data Output Y MSB Register Data Output Y LSB Register Data Output Z MSB Register Data Output Z LSB Register Status Register Identification Register A Identification Register B Identification Register C Table 5: Register List Register Access This section describes the process of reading from and writing to this device. The devices uses an address pointer to indicate which register location is to be read from or written to. These pointer locations are sent from the master to this slave device and succeed the 7-bit address plus 1 bit read/write identifier. To minimize the communication between the master and this device, the address pointer updated automatically without master intervention. This automatic address pointer update has two additional features. First when address 12 or higher is accessed the pointer updates to address 00 and secondly when address 0 is reached, the pointer rolls back to 9 address 03. Logically, the address pointer operation functions as shown below. If (address pointer = 09) then address pointer = 03 Else if (address pointer >= 12) then address pointer = 0 Else (address pointer) = (address pointer) + 1 The address pointer value itself cannot be read via the I C bus. Any attempt to read an invalid address location returns 0's, and any write to an invalid address location or an undefined bit within a valid address location is ignored by this device.
2
Access Read/Write Read/Write Read/Write Read Read Read Read Read Read Read Read Read Read
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HMC5843
Configuration Register A The configuration register is used to configure the device for setting the data output rate and measurement configuration. CRA0 through CRA7 indicate bit locations, with CRA denoting the bits that are in the configuration register. CRA7 denotes the first bit of the data stream. The number in parenthesis indicates the default value of that bit. CRA7 (0) CRA6 (0) CRA5 (0) CRA4 DO2 (1) CRA3 DO1 (0) CRA2 DO0 (0) CRA1 MS1 (0) CRA0 MS0 (0)
Table 6: Configuration Register A Location CRA7 to CRA5 CRA4 to CRA2 Name 0 DO2 to DO0 Description These bits must be cleared for correct operation. Data Output Rate Bits. These bits set the rate at which data is written to all three data output registers. Measurement Configuration Bits. These bits define the measurement flow of the device, specifically whether or not to incorporate an applied bias to the sensor into the measurement.
CRA1 to CRA0
MS1 to MS0
Table 7: Configuration Register A Bit Designations The Table below shows minimum output data rates given PVT conditions. All three channels shall be measured within a given data rate. DO2 0 0 0 0 1 1 1 1 DO1 0 0 1 1 0 0 1 1 DO0 0 1 0 1 0 1 0 1 Minimum Data Output Rate (Hz) 0.5 1 2 5 10 (default) 20 50 Not used Table 8: Data Output Rates
MS1 0
MS0 0
Mode Normal measurement configuration (default). In normal measurement configuration the device follows normal measurement flow. Pins BP and BN are left floating and high impedance. Positive bias configuration. In positive bias configuration, a positive current is forced across the resistive load on pins BP and BN. Negative bias configuration. In negative bias configuration, a negative current is forced across the resistive load on pins BP and BN. This configuration is not used. Table 9: Measurement Modes
0 1 1
1 0 1
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HMC5843
Configuration Register B The configuration register B for setting the device gain. CRB0 through CRB7 indicate bit locations, with CRB denoting the bits that are in the configuration register. CRB7 denotes the first bit of the data stream. The number in parenthesis indicates the default value of that bit. CRB7 GN2 (0) CRB6 GN1 (0) CRB5 GN0 (1) CRB4 (0) CRB3 (0) CRB2 (0) CRB1 (0) CRB0 (0)
Table 10: Configuration B Register
Location CRB7 to CRB5
Name GN2 to GN0
Description Gain Configuration Bits. These bits configure the gain for the device. The gain configuration is common for all channels. This bit must be cleared for correct operation.
CRB4 to CRB0
0
Table 11: Configuration Register B Bit Designations The table below shows nominal gain settings. Gain (counts/ milli-gauss) 1620 1300 970 780 530 460 390 280
GN2
GN1
GN0
Sensor Input Field Range:
Output Range
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0.7Ga 1.0Ga (default) 1.5Ga 2.0Ga 3.2Ga 3.8Ga 4.5Ga 6.5Ga (Not Recommended)
0xF800-0x07FF (-2048-2047 ) 0xF800-0x07FF (-2048-2047 ) 0xF800-0x07FF (-2048-2047 ) 0xF800-0x07FF (-2048-2047 ) 0xF800-0x07FF (-2048-2047 ) 0xF800-0x07FF (-2048-2047 ) 0xF800-0x07FF (-2048-2047 ) 0xF800-0x07FF (-2048-2047 )
Table 12: Gain Settings
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HMC5843
The resolution of the HMC5843 is based on the gain selection (zero to 7) and the influence of the analog power supply rail (AVDD). The following graph shows the interaction.
HMC5843 Resolution
12 Resolution (mGa) 10 8 6 4 2 2.4 2.6 2.8 3.0 AVDD (V) 3.2 Gain
0 1 2 3 4 5 6 7
Mode Register The mode register is an 8-bit register from which data can be read or to which data can be written. This register is used to select the operating mode of the device. MR0 through MR7 indicate bit locations, with MR denoting the bits that are in the mode register. MR7 denotes the first bit of the data stream. The number in parenthesis indicates the default value of that bit. MR7 (0) MR6 (0) MR5 (0) MR4 (0) MR3 (0) MR2 (0) MR1 MD1 (1) MR0 MD0 (0)
Table 14: Mode Register
Location MR7 to MR2 MR1 to MR0
Name 0 MD1 to MD0
Description These bits must be cleared for correct operation. Mode Select Bits. These bits select the operation mode of this device.
Table 15: Mode Register Bit Designations
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HMC5843
MD1 MD0 Mode Continuous-Conversion Mode. In continuous-conversion mode, the device continuously performs conversions an places the result in the data register. RDY goes high when new data is placed in all three registers. After a power-on or a write to the mode or configuration register, the first measurement set is available from all three data output registers after a period of 2/fDO and subsequent measurements are available at a frequency of fDO, where fDO is the frequency of data output. Single-Conversion Mode. When single-conversion mode is selected, device performs a single measurement, sets RDY high and returned to sleep mode. Mode register returns to sleep mode bit values. The measurement remains in the data output register and RDY remains high until the data output register is read or another conversion is performed. Idle Mode. Device is placed in idle mode. Sleep Mode. Device is placed in sleep mode. Table 16: Operating Modes Data Output X Registers A and B The data output X registers are two 8-bit registers, data output register A and data output register B. These registers store the measurement result from channel X. Data output X register A contains the MSB from the measurement result, and data output X register B contains the LSB from the measurement result. The value stored in these two registers is a 16-bit value in 2's complement form, whose range is 0xF800 to 0x07FF. DXRA0 through DXRA7 and DXRB0 through DXRB7 indicate bit locations, with DXRA and DXRB denoting the bits that are in the data output X registers. DXRA7 and DXRB7 denote the first bit of the data stream. The number in parenthesis indicates the default value of that bit. In the event the ADC reading overflows or underflows for the given channel, or if there is a math overflow during the bias measurement, this data register will contain the value -4096 in 2's complement form. This register value will clear when after the next valid measurement is made. DXRA7 (0) DXRB7 (0) DXRA6 (0) DXRB6 (0) DXRA5 (0) DXRB5 (0) DXRA4 (0) DXRB4 (0) DXRA3 (0) DXRB3 (0) DXRA2 (0) DXRB2 (0) DXRA1 (0) DXRB1 (0) DXRA0 (0) DXRB0 (0)
0
0
0
1
1 1
0 1
Table 17: Data Output X Registers A and B Data Output Y Registers A and B The data output Y registers are two 8 -bit registers, data output register A and data output register B. These registers store the measurement result from channel Y. Data output Y register A contains the MSB from the measurement result, and data output Y register B contains the LSB from the measurement result. The value stored in these two registers is a 16-bit value in 2's complement form, whose range is 0xF800 to 0x07FF. DYRA0 through DYRA7 and DYRB0 through DYRB7 indicate bit locations, with DYRA and DYRB denoting the bits that are in the data output Y registers. DYRA7 and DYRB7 denote the first bit of the data stream. The number in parenthesis indicates the default value of that bit. In the event the ADC reading overflows or underflows for the given channel, or if there is a math overflow during the bias measurement, this data register will contain the value -4096 in 2's complement form. This register value will clear when after the next valid measurement is made.
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HMC5843
DYRA7 (0) DYRB7 (0) DYRA6 (0) DYRB6 (0) DYRA5 (0) DYRB5 (0) DYRA4 (0) DYRB4 (0) DYRA3 (0) DYRB3 (0) DYRA2 (0) DYRB2 (0) DYRA1 (0) DYRB1 (0) DYRA0 (0) DYRB0 (0)
Table 18: Data Output Y Registers A and B Data Output Z Registers A and B The data output Z registers are two 8-bit registers, data output register A and data output register B. These registers store the measurement result from channel Z. Data output Z register A contains the MSB from the measurement result, and data output Z register B contains the LSB from the measurement result. The value stored in these two registers is a 16-bit value in 2's complement form, whose range is 0xF800 to 0x07FF. DZRA0 through DZRA7 and DZRB0 through DZRB7 indicate bit locations, with DZRA and DZRB denoting the bits that are in the data output Z registers. DZRA7 and DZRB7 denote the first bit of the data stream. The number in parenthesis indicates the default value of that bit. In the event the ADC reading overflows or underflows for the given channel, or if there is a math overflow during the bias measurement, this data register will contain the value -4096 in 2's complement form. This register value will clear when after the next valid measurement is made. DZRA7 (0) DZRB7 (0) DZRA6 (0) DZRB6 (0) DZRA5 (0) DZRB5 (0) DZRA4 (0) DZRB4 (0) DZRA3 (0) DZRB3 (0) DZRA2 (0) DZRB2 (0) DZRA1 (0) DZRB1 (0) DZRA0 (0) DZRB0 (0)
Table 19: Data Output Z Registers A and B Data Output Register Operation When one or more of the output registers are read, new data cannot be placed in any of the output data registers until all six data output registers are read. This requirement also impacts DRDY and RDY, which cannot be cleared until new data is placed in all the output registers. Status Register The status register is an 8 -bit read-only register. This register is used to indicate device status. SR0 through SR7 indicate bit locations, with S R denoting the bits that are in the status register. SR7 denotes the first bit of the data stream. SR7 (0) SR6 (0) SR5 (0) SR4 (0) SR3 (0) SR2 REN (0) SR1 LOCK (0) SR0 RDY(0)
Table 20: Status Register
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HMC5843
Location SR7 to SR3 SR2 Name 0 Description These bits must be cleared for correct operation. Regulator Enabled Bit. This bit is set when the internal voltage regulator is enabled. This bit is cleared when the internal regulator is disabled. Data output register lock. This bit is set when this some but not all for of the six data output registers have been read. When this bit is set, the six data output registers are locked and any new data will not be placed in these register until on of four conditions are met: one, all six have been read or the mode changed, two, a POR is issued, three, the mode is changed, or four, the measurement is changed. Ready Bit. Set when data is written to all six data registers. Cleared when device initiates a write to the data output registers, when in off mode, and after one or more of the data output registers are written to. When RDY bit is clear it shall remain cleared for a minimum of 5 s. DRDY pin can be used as an alternative to the status register for monitoring the device for conversion data. Table 21: Status Register Bit Designations Identification Register A The identification register A is used to identify the device. IRA0 through IRA7 indicate bit locations, with IRA denoting the bits that are in the identification register A. IRA7 denotes the first bit of the data stream. The number in parenthesis indicates the default value of that bit. The identification value for this device is stored in this register. This is a read-only register. Register values. ASCII value H IRA7 0 IRA6 1 IRA5 0 IRA4 0 IRA3 1 IRA2 0 IRA1 0 IRA0 0
REN
SR1
LOCK
SR0
RDY
Table 22: Identification Register A Default Values
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HMC5843
Identification Register B The identification register B is used to identify the device. IRB0 through IRB7 indicate bit locations, with IRB denoting the bits that are in the identification register A. IRB7 denotes the first bit of the data stream. Register values. ASCII value 4 IRB7 0 IRB6 0 IRB5 1 IRB4 1 IRB3 0 IRB2 1 IRB1 0 IRB0 0
Table 23: Identification Register B Default Values Identification Register C The identification register C is used to identify the device. IRC0 through IRC7 indicate bit locations, with IRC denoting the bits that are in the identification register A. IRC7 denotes the first bit of the data stream. Register values. ASCII value 3 IRC7 0 IRC6 0 IRC5 1 IRC4 1 IRC3 0 IRC2 0 IRC1 1 IRC0 1
Table 24: Identification Register C Default Values
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HMC5843
I2C COMMUNICATION PROTOCOL
The HMC5843 communicates via a two-wire I2C bus system as a slave device. The HMC5843 uses a simple protocol with the interface protocol defined by the I2C bus specification, and by this document. The data rate is at the standardmode 100kbps or 400kbps rates as defined in the I2C Bus Specifications. The bus bit format is an 8 -bit Data/Address send and a 1 -bit acknowledge bit. The format of the data bytes (payload) shall be case sensitive ASCII characters or binary data to the HMC5843 slave, and binary data returned. Negative binary values will be in two's complement form. The default (factory) HMC5843 7-bit slave address is 0x3C for write operations, or 0x3D for read operations. The HMC5843 Serial Clock (SCL) and Serial Data (SDA) lines have optional internal pull-up resistors, but require resistive pull-ups (Rp) between the master device (usually a host microprocessor) and the HMC5843. Pull-up resistance values of about 10k ohms are recommended with a nominal 1.8-volt digital supply voltage (DVDD). Other values may be used as defined in the I2C Bus Specifications or with the internal 50k ohm pull-up resistors (SDAP, SCLP) that can be tied to DVDD. The SCL and SDA lines in this bus specification can be connected to a host of devices. The bus can be a single master to multiple slaves, or it can be a multiple master configuration. All data transfers are initiated by the master device which is responsible for generating the clock signal, and the data transfers are 8 bit long. All devices are addressed by I2C's unique 7 bit address. After each 8-bit transfer, the master device generates a 9 th clock pulse, and releases the SDA line. The receiving device (addressed slave) will pull the SDA line low to acknowledge (ACK) the successful transfer or leave the SDA high to negative acknowledge (NACK). Per the I2C spec, all transitions in the SDA line must occur when SCL is low. This requirement leads to two unique conditions on the bus associated with the SDA transitions when SCL is high. Master device pulling the SDA line low while the SCL line is high indicates the Start (S) condition, and the Stop (P) condition is when the SDA line is pulled high while the SCL line is high. The I2C protocol also allows for the Restart condition in which the master device issues a second start condition without issuing a stop. All bus transactions begin with the master device issuing the start sequence followed by the slave address byte. The address byte contains the slave address; the upper 7 bits (bits7-1), and the Least Significant bit (LSb). The LSb of the address byte designates if the operation is a read (LSb=1) or a write (LSb=0). At the 9 th clock pulse, the receiving slave device will issue the ACK (or NACK). Following these bus events, the master will send data bytes for a write operation, or the slave will clock out data with a read operation. All bus transactions are terminated with the master issuing a stop sequence. I2C bus control can be implemented with either hardware logic or in software. Typical hardware designs will release the SDA and SCL lines as appropriate to allow the slave device to manipulate these lines. In a software implementation, care must be taken to perform these tasks in code.
OPERATIONAL EXAMPLES
The HMC5843 has a fairly quick stabilization time from no voltage to stable and ready for data retrieval. The nominal 5 milli-seconds with the factory default single measurement mode means that the six Bytes of magnetic data r gisters e (DXRA, DXRB, DYRA, DYRB, DZRA, and DZRB) are filled with a valid first measurement. To change the measurement mode to continuous measurement mode, after the 5 milli-second power-up time send the three bytes: 0x3C 0x02 0x00 This writes the 00 into the second register or mode register to switch from single to continuous measurement mode setting. With the data rate at the factory default of 10Hz updates (100 milli-seconds interval), a 100 milli-second delay should be made by the I2C master before querying the HMC5843 data registers for new measurements. To clock out the new data, send: 0x3D, and clock out DXRA, DXRB, DYRA, DYRB, DZRA, DZRB located in registers 3 through 8. The HMC5843 will automatically re-point back to register 3 for the next 0x3D query, expected 100 milli-seconds or later.
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HMC5843
SELF TEST OPERATION
To check the HMC5843 for proper operation, a self test feature in incorporated in which the sensor offset straps are excited to create a nominal field strength (bias field) to be measured. To implement this self test, the least significant bits (MS1 and MS0) of configuration register A are changed from 00 to 01 (0x12 or 0b000xxx01). By placing the mode register into single-conversion mode (0x01), two data acquisition cycles will be made on each magnetic vector. The first acquisition will be a set pulse followed shortly by measurement data of the external field. The second acquisition will have the offset strap excited in the positive bias mode (~5.5mA in offset straps) to create about a 0.55 gauss self test field plus the external field. The first acquisition values will be subtracted from the second acquisition, and the net measurement will be placed into the data output registers. If the configuration register B is left at the factory default value of 0x20, values around +715 ADC counts (0.55Ga * 1300 counts/Ga) will be placed in the data output registers. To leave the self test mode, change MS1 and MS0 bit of the configuration register A back to 0x00. Also change the mode register if single-conversion mode is not the intended next mode of operation.
SCALE FACTOR CALIBRATION
Using the method described above in section SELF TEST OPERATION, user can scale sensors' sensitivity to match each other. Since placing device in positive bias mode (or alternatively negative bias mode) applies the same artificial field on all three axis, the resulting ADC measurement in data output registers can be used to scale the sensors.
EXTERNAL CAPACITORS
The two external capacitors should be ceramic type construction with low ESR characteristics. Reservoir capacitor C1 is nominally 4.7 micro-farads in capacitance, with the set/reset capacitor C2 nominally 0.22 micro-farads in capacitance. Low ESR characteristics may not be in many smallest size SMT ceramic capacitors (0402), so be prepared to up-size the capacitors to gain Low ESR characteristics.
ORDERING INFORMATION
Ordering Number
HMC5843 HMC5843-TR HMC5843-demo HMC5843-eval
Product
3-Axis Digital Compass IC Tape and Reel 2.5k pieces/reel Demonstration Kit Evaluation Board
FIND OUT MORE
For more information on Honeywell's Magnetic Sensors visit us online at www.honeywell.com/magneticsensors or contact us at 800-323-8295 (763-954-2474 internationally).
The application circuits herein constitute typical usage and interface of Honeywell product. Honeywell does not warranty or assume liability of customerdesigned circuits derived from this description or depiction. Honeywell reserves the right to make changes to improve reliability, function or design. Honeywell does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. U.S. Patents 4,441,072, 4,533,872, 4,569,742, 4,681,812, 4,847,584 and 6,529,114 apply to the technology described
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Form #900367 February 2009 (c)2009 Honeywell International Inc.
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